The following is excerpted from the question-and-answer section of the transcript.
(Questions from industry analysts are provided in full, but answers are omitted - download the transcript to see the full question-and-answer session)
Question: Harlan Sur - JP Morgan - Analyst
: Yes, thank you for that, and that was a great overview of the UALink technology opportunities, some of the challenges that you're trying to
address with UALink that the industry faces. So I appreciate the great overview by you and Chris. As you mentioned, I've got a few follow-up
questions for the team while we have a few minutes left here.
So I'll start off with when the team introduced your Scorpio family of PCIe and XPU fabric switching products in October of last year, right?
You quantified the four-year market opportunity at around $5 billion. How does that break out PCIe switching versus XPU fabric switching.
And within that, how big do you think the opportunity is for UALink?
Question: Harlan Sur - JP Morgan - Analyst
: And then my second question, the outlined many benefits of the UALink standard for scale-up connectivity applications. If you can just
highlight. Maybe the top 1 or 2 key attributes that that that you believe will ultimately drive the proliferation of the UALink protocol.
Question: Harlan Sur - JP Morgan - Analyst
: Perfect. And then you had mentioned the quick time to market as it relates to incorporation of the UALink consortium, all the way to the
recent ratification of the 200-gigabit per second 10 specification that was released in April. Do you believe that the adoption of UALink will
happen with the 1.0 specification or that was released in April, or is the industry you think going to need additional updates. That are
potentially going to be required to drive a more prolific adoption of UALink.
Question: Harlan Sur - JP Morgan - Analyst
: That's perfect. And then going back to the initial discussion and good to see the recent support and participation by the Astera team on the
announcement of Nvidia introducing its NVLink fusion, right? Essentially offering his scale up NVLink architecture, IP chiplets to be integrated
into non NVIDIA based XPUs and Obviously, Astera is an ecosystem partner to NV fusion.
Can you guys just talk a little bit about that announcement, what it means for, I know that you talked about the chiplet I/O architecture that
you're going to use to offer as a part of the NVLink fusion portfolio. But can you guys just talk about the announcement and what it means
from a UALink initiative perspective? And what it means for just overall scale up connectivity segment of the market.
Question: Harlan Sur - JP Morgan - Analyst
: Yes. And I would agree with you that there's multiple optionality for your customers, although I would also agree that the bias over time
would be towards more open architectures like the UALink protocol. That being said, there was a recent announcement of a new type of
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MAY 20, 2025 / 8:30PM, ALAB.OQ - Astera Labs Inc Webinar: Vision for Expanding Opportunities in AI
Infrastructure with UALink
scale up architecture also open as well called the scale up Ethernet or SUE protocol. I'm just wondering how does the UALink protocol
compare with this recently introduced the scale up Ethernet architecture.
Question: Harlan Sur - JP Morgan - Analyst
: And you guys talked about the merits of UALink standard, right, but can you just maybe a little bit of a deeper dive into why the Astera team
is specifically well positioned to deliver solutions to support the ecosystem? What products are you planning to introduce? And more
importantly, when do you believe systems based on UALink will be introduced and deployed, in volume scale?
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